Nowadays, most electronic systems need to support hot plugging function, which refers to the process of plugging and unplugging a certain unit of the system while it is working normally, without any impact on the system.
The impact of hot plugging on the system is significant in two aspects:
Firstly, during hot plugging, the mechanical contacts of the connector will bounce at the moment of contact, causing power oscillation. This oscillation process can cause the system power to drop, resulting in errors or system restarts, and may also cause the connector to ignite, leading to a fire. The solution is to delay the power on time of the connector. During the ten milliseconds when the connector shakes (t1 to t2), do not power on the connector. Wait until the insertion is stable (after t2) before powering on, which is known as anti shake delay.
Secondly, during hot plugging, due to the charging effect of the system's large capacity energy storage capacitor, there will be a significant surge current in the system. As we all know, the current of the capacitor decreases exponentially during charging (as shown in the bottom left figure), so the surge current is very large at the beginning of charging. This surge current may burn out the power fuse of the equipment, so it is necessary to control the surge current during hot plugging to make it change according to the ideal trend, as shown in the upper right figure, where 0~t1 is the slow start time of the power supply.
In summary, the important purpose of a slow start circuit is to achieve two functions:
1) Anti shake delay power on;
2) Control the rising slope and amplitude of the input current.
There are two types of slow start circuits: voltage slope type and current slope type.
The voltage slope type slow start circuit has a simple structure, but its output current is greatly affected by the load impedance, while the output current of the current slope type slow start circuit is not affected by the load, but the circuit structure is complex.
The following focuses on the voltage type slow start circuit.
MOS transistors are commonly used in the design of slow start circuits. MOS transistors have the characteristics of low conduction impedance Rds and simple driving. Adding a small number of components around them can form a slow start circuit. Normally, pMOS is used in positive power supply and NMOS is used in negative power supply.
1) D1 is an embedded diode to prevent damage to the secondary circuit caused by excessive input voltage;
2) The purpose of R2 and C1 is to achieve anti jitter delay function. In practical applications, R2 is generally selected as 20K ohms, and C1 is selected as around 4.7uF;
3) The purpose of R1 is to provide a fast discharge channel for C1, and it is required that the voltage division value of R1 is greater than the voltage stabilization value of D3. In practical applications, R1 is generally selected to be around 10K;
4) R3 and C2 are used to control the rising slope of the power on current. In practical applications, R3 is generally selected to be around 200K ohms, and C2 has a value of 10nF~100nF;
5) The purpose of R4 and R5 is to prevent self-excited oscillation of MOS transistors, and R4 R5lt;
6) The purpose of embedded diode D3 is to protect the gate source of MOS transistor Q1 from high voltage breakdown; The purpose of D2 is to isolate the anti jitter delay circuit composed of R2 and C1 and the power on slope control circuit composed of R3 and C2 after the MOS transistor is turned on, to prevent the MOS gate charging process from being affected by C1.
Let's analyze the slow start principle of the circuit below:
Assuming that the parasitic capacitance between the gate and source of MOS transistor Q1 is Cgs, the parasitic capacitance between the gate and drain is Cgd, and the parasitic capacitance between the drain and source is Cds, and a capacitor C2 (C2gt;>Cgd) is connected in parallel outside the gate drain, the total capacitance of the gate drain is Cgd=C2+Cgd. Since the capacitance value of Cgd is almost negligible with respect to C2, the turn-on voltage of the MOS transistor gate is Vth, and the gate source voltage of the MOS transistor is Vw (which is equal to the embedded voltage of the voltage regulator D3) during normal operation, the time constant for charging capacitor C1 is t=(R1//R2//R3) C1. Due to R3, the capacitance value of Cgd is almost negligible. Usually much larger than R1 and R2, so t (R1//R2) C1.
The working principle of the voltage slow start circuit mentioned above will be analyzed in three stages:
Phase 1:- The 48V power supply charges C1, and the charging formula is as follows.
Uc=48*R1/（R1+R2）［1-exp（-T/t）］， Where T is the time it takes for the voltage of capacitor C1 to rise to Uc, with a time constant t=(R1//R2) C1. So, the time required from power on to MOS transistor turn-on is: Tth=-t*ln［1-（Uc*（R1+R2）/（48*R1））］
Phase 2: After the MOS transistor is turned on, the drain current begins to increase, and its rate of change is proportional to the transconductance and gate source voltage change rate of the MOS transistor. The specific relationship is: dIdrain/dt=gfm*dVgs/dt， Among them, gfm is the transconductance of the MOS transistor, which is a fixed value, Idrain is the drain current, and Vgs is the gate source voltage of the MOS transistor. During this period, it is reflected in the constant control of the drain source current by the gate source voltage. MOS transistors are classified as voltage controlled devices because of this.
Phase 3: When the drain source current Idrain reaches the maximum load current, the drain source voltage also reaches saturation, and at the same time, the gate source voltage enters the plateau period, with a voltage amplitude of Vplt. Due to the constant leakage source current Ids and gate source voltage Vplt=Vth+(Ids/gfm) during this period, and the fixed gate source voltage causing all gate currents to pass through the feedback capacitor Cgd, the gate current is Ig=(Vw Vplt)/(R3+R5). Since R5 is negligible with respect to R3, Ig (Vw Vplt)/R3. Due to the gate current IgIcgd, Icgd=Cgd*dVgd/dt。 Due to the constant gate source voltage during this period, the rate of change of the gate source voltage and the drain source voltage is equal. Therefore, there are: dVds/dt=dVgd/dt=（Vw-Vplt）/（R3*C2）。 From this formula, it can be concluded that the slope of the change in drain source voltage is related to the value of R3 * C2. For a system with a constant load, as long as the value of R3 * C2 is controlled, the rising slope of the hot plug surge current can be controlled.
The schematic diagram of the changes in gate source voltage Vgs, drain source voltage Vds, and drain source current Ids during the slow start phase is shown below.
During the 0-t1 stage, Schottky diode D2 has not yet turned on, so Vgs is equal to 0. During this period- The 48V power supply charges C2 through R3 and R5. When the voltage of C2 rises to the turn-on voltage of D2, the gate voltage of the MOS transistor begins to rise. When the gate source voltage rises to the turn-on voltage Vth of the MOS transistor, the MOS transistor conducts and the drain source current Ids begins to increase. When the gate source voltage of the MOS transistor rises to the platform voltage Vplt, the drain source current Ids also reaches its maximum. At this point, the drain source voltage Vds enters saturation and begins to decrease. When the platform voltage Vplt ends, the MOS transistor is completely conductive, the drain source voltage drops to the lowest, and the on resistance Rds of the MOS transistor is minimized.
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